end komponent;
er komponent shiftersright_stage4
Port (in35: i STD_LOGIC_VECTOR (7 downto 0);
stage4right: i std_logic;
out20: out STD_LOGIC_VECTOR (7 downto 0));
end komponent;
begynne
shiftright0: shiftersright_stage1 port map (D, E
(0), signa15);
shiftright1: shiftersright_stage2 port map (signa15, E (1 ), signa16);
shiftright2: shiftersright_stage4 port map (signa16, E
(2), zact);
outright
zeroact
når zact = "00000000" Anmeldelser
annet '0';
ende strukturelle; Anmeldelser